Electrical apparatus



Um. R W59 m. w. REACH, .JR

ELECTRICAL APPARATUS Filed July 29, 1957 l mfg 7,4/3

INVENTOR. 50)??54671 JA?. BY

ATTORNEY United States Patent O ELEETRICAL APPARATUS Roy W. Reach, Jr., Sudbury, Mass., assignor, by mesne assignments, to Minneapolis-Honeywell Regulator Company, a corporation of Delaware Application July 29, 1957, Serial No. 674,790

12 Claims. (Cl. 340-174) A general object of the present invention is to provide a new and improved electrical apparatus useful in controlling the selection of information from a magnetic core element storage array. More specifically, the present invention is concerned with an apparatus for selecting one of a plurality of magnetic core elements from a magnetic core memory array which apparatus is characterized by its simplicity, its adaptability to produce uniform selection signals for the circuits, and its reliability.

Bistable magnetic core elements are receiving wide application in the eld of digital data storage. These elements are frequently arranged in three dimensional arrays so that large amounts of digital data may be selectively stored in various locations in the array. The selection of any one particular core in an array is generally accomplished on a two dimensional basis by means of select wires which pass through the array. The core elements and the select wires are so arranged that each core element is uniquely defined by two different select wires which pass through the array. When a half select current is applied to two wires intersecting one core element, the element may be shifted from one bistable state to the other. This is sometimes referred to as a coincident current selection. 1

An article describing the use of magnetic core elements in a coincident current type memory has been published by I. W. Forrester in the Journal of Applied Physics, January 195.1, page 44. The article is entitled, Digital Information Storage in Three Dimensions Using Magnetic Cores.

The present invention is adapted to be utilized with a magnetic core element array of the type described in the Forrester article and comprises new and improved circuitry for selecting the cores in the array. In order to minimize the equipment required in the selection `of a `core from an array, the present invention comprises p a circuit wherein it is possible to utilize a single voltage source from which constant current selection signals may be derived. Each selection signal is derived for use in two dimensions of the array. Thus, a single current pulse generated by the circuitry may be applied to the two selection wires associated with one particular core element in `the array. t

It is accordingly another more specific object of the present invention to provide a new and improved selection circuit for a two dimensional memory array wherein the two selection wires for selecting any one core in the array are adapted to be energized by the same signal source. v

The foregoing object is achieved by` a pulse generating circuit which includes a power source which has a substantially constant current drain and where the current ilow in the circuit may be selectively diverted from an inactive circuit to an active selection circuit in the array when a core element selection is to be made. This signal generating circuit utilizes a current sinkwhich normally draws current from the power source through an ice inductor. Switching means are provided whereby the current ow may be selectively diverted in one direction or another through predetermined selection paths in the array in order to perform reading and writing functions.

A still further object of the present invention is, therefore, to provide a new and improved selection circuit for a core memory array wherein a power source is provided with a substantially constant current drain and switching means are eiective to divert the current from the power source through selected paths in the array.

The elements most conveniently used in the switching circuits of the array are transistor devices. Inasmuch as the current owing in the selection wires must be able to flow in a forward or reverse direction, additional switching elements are required and these conveniently take the form of symmetrically conducting transistor devices so arranged that they may be activated for controlling the selection of the paths for the selecting currents in the memory array.

It is then a still further object of the present invention to provide a new and improved selection circuit for a memory array using transistor devices as the switching elements thereof, wherein selected ones of said switching devices are symmetrically conducting in order to select the paths for selection currents in the array.

The foregoing objects and features of novelty which characterize the invention as well as other objects of the invention are pointed out with particularity in the claims annexed to and forming a part of the present specification. For a better understanding of the invention, its advantages and specic objects attained with its use, reference should be had to the accompanying drawings and' descriptive matter in which there is illustrated and described a preferred embodiment of the invention.

Of the drawings:

Figure 1 is a schematic showing of one form of memory array and the selection circuits therefor;

Figure 2 illustrates schematically the basic wiring nor-` mally associated with each core element of the array of Figure 1; and

Figure 3 illustrates a modified schematic for a current source for a memory array.

Referring rst to Figure l, the numeral 10 identities a two dimensional array incorporating a plurality of magnetic core elements. The core array 10 has a plurality of horizontal selection wires X1-X7 and a plurality of vertical selection wires Y1-Y6. In series with each individual selection wire is a symmetrically conducting transistor. The transistors for the horizontal selection wires are transistors 'FX1-TXT The transistors for the vertical selection wires are TY1-TY6. These symmetrically conducting transistors each have a base or control element, and a pair of output electrodes so arranged. that the current will ilow between these electrodes in either direction under the control of a signal applied to the base electrode. One type of transistor available commercially is the Sylvania type 6T847. In order to provide a selection signal source for the array, there is provided a voltage source V having a positive terminal 11 and a negative terminal 12. Connected in series with the voltage source V between the terminals 11 and 12 are a pair of series circuits, the first of which includes a resistor 13, inductor 14, a diode 15 and a current sink 16. The current sink comprises a condenser 17, a resistor 18 and may additionally include a battery or other relatively lo'w voltage source 19, the latter being used under conditions of heavy duty cycle operation. The second series circuit is also connected to the supply terminals 11 and 12 and this includes a resistor 20, an inductor 21, a diode 22 and the current sink 16.

In order to control the direction of the current tiow through' the array 10, there are provided a pair of tran asi'mar Y l lsist'or switches 25 and 26. Each of these transistor switches incorporates the usual base, emitter and collector electrodes. The emitter-collector electrode path of the transistor 25 is connected to selectively shunt the diode and the current sink 16 when it is desired to perform a read operation in the array 10. The emitter-collector electrode path of the transistor 26 is adapted to shunt the diode 22 and current sink 16 when it is desired to perform a write operation.

Normally, the transistors 25 and 26 are both biased to cut-olf by a positive biasing source. In order to switch one or the other of the transistors, a negative pulse will be applied to one or the other of the transistors depending upon whether a read or write operation is to take place. A representative wave form for this is shown in connection with base electrodes of the read transistor 25 and the write transistor 26. Thus the normal biasing voltage is +V@ and the negative source during the switching pulse is indicated by voltage Vg The selection transistors for the horizontal and vertical selection wires are all substantially the same and a repre-V sentative input circuit is that illustrated in conjunction with a transistor TY 6. In this instance, a positive biasing voltage -l-'VB is applied to the'base electrode of the transistor. A diode 27 is also coupled to the base electrode with the anode thereof connected to the base of transistor TYS and the cathode serving as an input terminal for the selection signal. The bias on the input selection terminal will Vnormally be -V1. In order to render the transistorsaturated the voltage is switched to -l-VZ.

before considering the. over-all functioning of the cir-V cuitry of Figure l, reference should be had to Figure 2 toillustrate the fundamental circuitry normally associated with each corev element of the array 10. In Figure 2, a core ,element 30 is shown as having a horizontal selection wire X, vertical selection Wire. Y, a plane selection wire Z; 'and a sense wire S. The core 39 is presumed `to be a core havingv a rectangular' hysteresis characteristic and having substantial residual ux such that it may be considered asV being a bistable core. In order to switch the core from one bistable'state to the other, it is necessary Yto apply a half select current to the X select wire and a further half select current to the Y select wire. It is assumed that in applying the half select signals to the X and Y wires the resultant current will be effective to switch the core 30 from a zero state to a one state. By reversing the directionI of the current iiow in the X andl Y1 wires and again applying half select currents to Cach of these wires, the core 30 may be switched back to its other bistable state. In order to inhibit the switching O the core,'a further half select current may be applied to the Z select wire where the polarity of the signal is opposite that appearing on the X and Y wires. When ever` the core 30 is switched, a signal will be induced in the sense wire S. For ease of illustrating the present invention, the Z select wire and the sense wire S have been eliminated from Figure l. It should be understood, however, that a complete circuit would incorporate these additional Z and S wires. The aforementioned article of Forrester should be referred to for a more exacting treatise on the details of these cores and the relationship of the select wires and sense wires with respect to the cores.

Inrconsidering the over-all operationof the circuit of Eigure l, it is iirst assumed that asteadyvstate condition exists wherein ng read signals or write signals are present. Under these conditions, a current will be flowing from the positive terminal 11 of the voltage source V through the current sink, the diodes 15 and 22, and the remaining portion of the series circuits which includes for the diode: 15 the inductor 14 and resistor 13; and for diode 22 inciudes the inductor 21 and resistor 20. Under these conditions, no current will beowing through any of the selection wires in the array 1u. .Y

If it isvdesired to perform a read operation, a read signal, illustrated in the drawing as a negative signal pulse, will be applied to the transistor 25 to switch the transistor from its nonconductive region to its saturated region to thereby apply a ground to the cathode side of the diode 15. This will mean that all of the current llow normally flowing through the diode 15 and the sink 16 by way of the inductor 14 and resistor 13 will now be shunted through the emitter-collector circuit of the transistor 25. With this'unbalance in the circuit, the current ow through the diode 22 will be diverted into the array 1). It is assumed that the selection transistors TYl and TX1 have selection signals applied thereto so that both of these transistors are operating in their saturated or low impedance region. Thus, a current flow path may be traced through the array which originates from the ground terminal (or positive terminal) 11 of the voltage source V through the collector-emitter path of the transistor 25 selection wire X1, transistor TXI, transistor TYl, selection wire Y1, inductor 21 and resistor 20 back to the negative terminal 12. The current will ilow in this path and will select the core inthe array 10 which is located at the intersection of the X1 and Y1 wires. No other core in the array will be selected as only half currents will be applied thereto or no current at all will be applied. Further, the inductor 21 and resistor 2t) tend to hold the current ow through the array constant during the selection operation. A representative time length for the cur- Y rent pulse is 2.45 microseconds.

' at all times, the amount of transient regulation required of this source is considerably minimized. Y

When a writing operation is to take place, a write pulse is applied to the transistor 26. This transistor will be switchedfrom its nonconducting region into its saturated region to effectively shunt the current flowing through the diode 22 to the inductor 21 to ground. At the same time, the switch will be effective to drop the voltage on the diode 15 so that it is no longerconductingy to thereby divert the current into the array. The current flow through the array may be traced from the positive terminal 11 of the voltage terminal V through the emitter-collector path of the transistor 26 to the selection wire Y1, selection transistor TY1, selectionV transistor TX1, selection wire X1, inductor 14 and resistor 13 to the negative terminal 12. It will be noted that the current llow traced for the writing operation is opposite that for the read operation so that itis possible to set the core by this write signal. As with the read" operation, the select signals have been diverted from a common source to both horizontal and vertical selection wires to thereby minimize the circuitry required in performing a write operation.

Referring now to Figure 3, a simplied core array 35 has been illustrated incorporating only four cores. This array is assumed to be of the same type as that of the array 10 of Eigure l except that the number of cores illustrated has been minimized. In the circuit of Figure 3, the current source for supplying the select signals for the array 35 has been changed from the direct coupled circuit of Figure l to a transformer coupled pulse generating circuit. Added to the circuit of Figure 3 is a transformer 36 having a Vsecondary winding 37 used to supply the current signal to the array 35. The primary winding 38 is arranged Awith aV constant current signal generating circuit connected thereto. This circuit comprises a voltage supply circuit V5 having connected thereto a first series circuit which comprises a current sink 40, a diode 41, an inductor 42, and resistor 43. Connected between the inductor 42 and diode 41 is a connection to a center tap 44 on the primary 38. The diversion of the current flowing in this series circuit may be effected by a pair of transistors 45 and 46. The transistor 45 may be termed the read transistor while the transistor 46 may be termed the write transistor, `each #of said transistors being adapted to be selectively iswitched to a low impedance state in order to control the direction of the current diversion through the primary winding 38 into the secondary 37. This particular current generating circuit is more fullydescribed and claimed `lin a co-pending application of Roy W. Reach, Jr. et al. entitled Electrical Apparatus filed concurrently herewith. For purposes of explanation in conjunction with Figure 3, the current generating circuit is adapted to produce constant current pulses in the secondary winding 37, where the polarity of the pulses may be reversed Lin accordance with whether a read or write operation `is to take place.

As with Figure 1, the selection circuit of Figure 3 is eso arranged that a current pulse in the secondary windting 37 will be effective to pass through both the hori- ,zontal and vertical selection wires selected. Thus if the transistor TX1 and the transistor TYl are active at the same time, current will pass from the upper terminal of the secondary 37 to the transistor TYI, the selection -wire Y1, the transistor TXl and the select wire X1 to .the ground terminal back to the lower terminal of the xsecondary 37.

If the polarity of the signal in the secondary 37 is sreversed, the current flow will be in the opposite direc- Ition through the array 35 with the path being selected tby the particular X and Y selection transistors which are activated.

It will thus be seen that the circuit of Figure 3 utilizes 'the series selection technique of Figure l wherein current ilows through the array in both dimensions originating from a single source. Thus, this circuit likewise minimizes the amount of circuitry required in order to effect the desired selection of a core in the array.

While, in accordance with the provisions of the statutes, there has been illustrated and described the best forms of the invention known, it will be apparent to those skilled in the art that changes may be made in the apparatus described without departing from the spirit of theinvention as set forth in the appended claims and that insome cases, certain features of the invention may be used to advantage without a corresponding use of other features.

Having now described the invention, what is claimed as new and novel and for which it is desired to secure by Letters Patent is:

1. Electrical apparatus for selectively switching one of a plurality of bistable magnetic elements in a matrix comprising a plurality of selection wires positioned with respect to said elements so that each element is uniquely defined by the presence of two of said selection wires, a signal source, rst switching means connecting said signal source and two of said selection wires in a series circuit to said signal source, said tirst switching means comprising a pair of symmetrically conducting devices connected to define the two selection wires to be activated by said signal source and second switching means connected to said first switching means to control the direction of current flow through said first switching means, said second switching means comprising a pair of asymmetrically conducting switching devices.

2. Electrical apparatus for selectively switching one of a plurality of bistable magnetic elements in a matrix comprising a plurality of selection wires positioned with respect to said elements so that each element is uniquely defined by the presence of two of said selection wires, .a signal source, a first pair of symmetrically conducting amava? transistor switching means connecting said signal source and two of said selection wires in a single series circuit to said signal source and a second pair ot asymmetrically conducting transistor switching means connected to said signal source to control the direction of current llowing in said first pair of switching means.

3. Apparatus for selectively switching bistable magnetic core elements in a memory array having a plurality of vertical selection wires and a plurality of horizontal selection wires with a magnetic core element uniquely positioned at the intersecting points of each horizontal and each vertical selection wire, a symmetrically conducting switching means connected in series with each selection wire, a constant current selection signal source, asymmetrically conducting switching means connected to said signal source to control the effective direction of current ow therefrom to said array, and means including said symmetrically conducting switching means connecting a selected horizontal selection wire and a selected vertical selection wire in series to said signal source.

4. Apparatus for selectively switching bistable magnetic core elements in a memory array having a plurality of vertical selection wires and a plurality of .horizontal selection wires with a magnetic core` element uniquely positioned at the intersecting points of each horizontal and each vertical selection wire, switching means connected in series with each selection wire, a selection signal source, said signal source comprising a constant current pulse generator having a current sink from which current may be diverted to said selection wires, and means including said `switching means connecting a selected horizontal selection wire and a selected vertical selection wire in series to said signal source.

5. A constant current signal source for a two dimensional bistable magnetic element array comprising a cur rent sink, a source of power, a pair of series circuits each comprising a diode, an inductor, and a resistor, and a pair of switching means connected one each to said pair of series circuits, said switching means being adapted to selectively divert the current llowing `to said current sink into said array in aiirst or a second direction.

6. A constant current signal source for a two dimensional bistable magnetic element array comprising a current sink, said current `sink comprising a parallel connected resistor, condenser, and D.C. potential source, a further source of power, a pair of series circuits each comprising a diode, an inductor, and a resistor, and a pair of switching means connected `one each to said pair of series circuits, said switching means `being adapted to selectively divert the current flowing to said current sink from said further source of power into said array in a rst or a second direction.

7. A constant current signal source for a two dimensional bistable magnetic element array comprising a current sink, a source of power, a pair of series circuits each comprising a diode, an inductor, and a resistor, a pair of switching means connected one each to said pair of series circuits, said switching means being adapted to selectively divert the current llowing to said current sink through said array in a first or a second direction, and a further plurality of switching means connected to said array, said further switching means operating in pairs to selectively direct the current flow in said array.

8. A circuit for switching a bistable magnetic core element comprising a pair of select lines adapted to intersect said element, a pair of symmetrical transistor switches connected in series with the respective pair of select lines, a select signal source, and means connecting said pair of select lines and said pair of switches in series to said signal source.

9. A circuit for switching a bistable magnetic core element comprising a pair of select lines adapted to intersect said element, a pair of symmetrical switches connected in series with the respective pair of select lines, a select signal source, said select signal source comprising a source of power having an inductor, an asymmetrically conducting device and a current sink connected in series and an electronic switch connected to divert the current away from said current sink to said select lines, and means connecting said pair of select lines and said pair of switches in series to said signal source.

l0. Apparatus for selectively switching bistable core elements in a twordimensional array comprising a plu rality of first dimensionjselection lines, a plurality'of second dimension selection lines, said first and second dimension selection lines being positioned in said array toV uniquely dene a core element location at the intersection-of each line of each dimension, means connecting one end of each of said plurality of selection lines in said first dimension to Ya first common line, a first plurality of symmetrically conducting switches connecting the other end of eachy of said plurality of selection lines in said first dimension to a second common line, means connecting one end of each of said plurality of selection lines in said second dimension to a third common line, a second plurality of symmetrically conducting switches connecting the otherA end of each of said plurality of selection lines in said second dimension to a fourth common line, a source of power, a current sink, a first inductor connected to said source of power and to said first common line, a first diode connected to said first inductor and to said current sink, a second inductor connected to said source of power and to said second common line, a second diode connected to said second inductor and to said current sink, a read switch connected to said first common line, a write switch connected to said vsecond common line, and means connecting said third and Vsaid fourth common lines togetherf ll. Apparatus for selectively switchingvbistable core elements in a two dimensional array comprising a plurality of first dimension selection lines, a plurality of second dimension selection lines, said first and second dimension selection lines being positioned in said array tol uniquely define a core element location at the intersection of each line of each dimension, means connecting one'end of each of said plurality of selection lines in said first dimension to a first common line,a first plu rality of symmetrically conducting transistor switches connecting the other end of each of said plurality of selection lines in said first dimension to a second common line, means connecting one end of each of said plurality of selection lines in said second dimension to a third common line, a second. plurality of symmetrically conducting transistor switches connecting the other end of each of said plurality of selection lines in said second dimension to a fourth common line, a source of power, a current sink comprising a parallel connected Vresistor andcondenser, a first inductor connected to said source of power and to said rst common line, a first diode con-A nected to said first inductor and toH said current sink, 'a secondV inductor connected to said source of power and to said second common line, a second diode connected to said second inductor and to said current sink, a read transistor switch connected to said first common line, a` write transistor switch connected to said second common line, and means connecting said third and said fourth common lines together.

12V. Apparatus for selectively switching bistable core elements ina two dimensional array comprising a plu-V rality of first dimension selection lines, a plurality of second dimension selection lines, said first and second dimension selection lines being positioned in said array to uniquely define a core element location at the inter-- section of each line of each dimension, means connecting one end of each of said plurality of selection lines inv said first dimension to a first common line, a first plu-v one end to said source of power, a first inductor con-r nected to said source ,of power and to said first common line, a first diode connected to said first inductor and to the other end of said current sink, a second inductor connected to said source of power and to said second common line, a second diode connected to said seiond inductor and to said other end of said current sink, a read switch connected to said first common line and to said one end of said current sink, a write switch connected to said second common line and to said one end of said current sink, and means connecting said thirdl and said fourth common lines together. i

References Cited in the file of this patent UNITED STATES PATENTS 2,629,834` Trent Feb. 24, 1953 2,700,150 Wales Jan. 18, 1955 2,824,697 Pittman Feb. 25, 1958 

